The present invention relates in general to substrate manufacturing technologies and in particular to methods and apparatus for the optimization of photo resist.
In the processing of a substrate, e.g., a semiconductor substrate or a glass panel such as one used in flat panel display manufacturing, plasma is often employed. As part of the processing of a substrate for example, the substrate is divided into a plurality of dies, or rectangular areas, each of which will become an integrated circuit. The substrate is then processed in a series of steps in which materials are selectively removed (etching) and deposited (deposition) in order to form electrical components thereon.
In an exemplary plasma process, a substrate is coated with a thin film of hardened emulsion (i.e., such as a photo resist mask) prior to etching. Areas of the hardened emulsion are then selectively removed, causing parts of the underlying layer to become exposed. The substrate is then placed in a plasma processing chamber on a substrate support structure comprising a mono-polar or bi-polar electrode, called a chuck or pedestal. Appropriate etchant source are then flowed into the chamber and struck to form a plasma to etch exposed areas of the substrate.
Among the most common substrate manufacturing approaches are dual damascene substrates. In one example, called Via-First, the substrate is first coated with photo resist and then the vias are lithographically patterned. Next, an anisotropic etch cuts through the surface hard mask and etches down through the dielectric layers (such as silicon oxide, low-K materials) of the substrate, and stops on a barrier (such as silicon nitride, silicon carbide), just above the underlying metal layer. Next, the via photo resist layer is stripped, and the trench photo resist is applied and lithographically patterned. Some of the photo resist will remain in the bottom of the via and prevent the lower portion via from being over-etched during the trench etch process. A second anisotropic etch then cuts through the surface hard mask and down through the low K material, stopping at the embedded hard mask. This etch forms the trench. The photo resist is then stripped and the Silicon Nitride barrier at the bottom of the via is opened with a very soft, low-energy etch that will not cause the underlying copper to sputter into the via. As described above, the trench and via are filled with a conductive material (e.g., aluminum (Al), Copper (Cu), etc.) and polished by chemical mechanical polishing (CMP).
In another example, called trench-first. In one example, the substrate is coated with photo resist and a trench lithographic pattern is applied. An anisotropic dry etch then cuts through the surface hard mask (again typically plasma silicon nitride), and down through the low-k dielectric, stopping on the embedded etch stop layer (also typically silicon nitride). The photo resist is then stripped, leaving behind a trench. Next, the substrate is again coated with photo resist and a via lithographic pattern is applied. The via etch then cuts through the embedded etch stop layer to the final silicon nitride barrier located at the bottom of the via. The bottom barrier is then opened with a special etch and the photo resist is stripped.
In these, and other substrate processing methodologies, photo resist may be employed in order to prevent over-etching of particular substrate features (e.g., plug, trench, via, etc.). For example, when the photo resist is added as a blanket and then etched back, such as when trenches are being formed for dual-damascene structures, it is fairly difficult to apply a perfectly uniform layer of photo resist. Because underlying structures are already present on the substrate, photo resist tends to form in a topographic pattern, creating hills and valleys. As photo resist is etched away, areas on the substrate with a higher topography take longer to etch than areas with a lower topography. Subsequently, non-uniform photo resist profiles among the trenches may be created, potentially causing quality problems. This generally requires that either the plasma process is optimized for the lower topography, in which excess PR remains in areas of high topography, or the plasma process is optimized for higher topography, in which over etching can potentially occur in a feature.
It is generally believed in the art that a fluorine-based etchant should not used to etch photo resist, since it tends to also have a low substrate selectivity. Steve Lassig, et al., Selective Removal Strategies for Low k Dual Damascene, Semiconductor Fabtech, pp 185–190 (2001), discusses the addition of small amounts of a fluorine containing gas during various etch processes (e.g., oxide, dual damascene, etc.) in order to facilitate residue removal. In general, etch processes often leave polymer-like films and residues that must be removed along with the remaining photoresist material. The addition of small quantities of a fluorocarbon gas, such as CF4, may be added to facilitate residue removal with little impact on critical dimensions (CD). However, use of a fluorine containing gas during blanket photo resist etching has generally been avoided in the art, since it may also attack and potentially damage previously created features on the substrate surface.
FIGS. 1A–B show an idealized cross-sectional view of a substrate with a blanket of photo resist. In the discussions that follow, terms such as “above” and “below,” which may be employed herein to discuss the spatial relationship among the layers, may, but need not always, denote a direct contact between the layers involved. It should be noted that other additional layers above, below, or between the layers shown may be present. The terms center and edge refer to relative positions on the surface of the substrate, with the edge portion being placed closer to the edge ring than the center portion. Furthermore, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
Referring now to FIG. 1A, an idealized cross-sectional view of a substrate is shown. At the bottom of the substrate, there is shown a layer 108, typically comprising SiO2. Above layer 108 is disposed a barrier layer 104, typically comprising nitride or carbide (SiN or SiC). Dual damascene substrates further comprise a set of metal layers 109, typically comprising aluminum or copper, and a set of trenches or vias 114 which tend to be clustered in dense areas 115 or isolated in isolated areas 116. Above the barrier layer 104, is disposed a intermediate dielectric (IMD) layer 106, comprising a low K material (e.g., Coral, etc.). Above the IMD layer 106, there may be placed a cap layer 103, typically comprising SiO2. Above cap layer 103, there may be disposed a photo resist blanket 102. The substrate is further divided into a center portion 110 and an edge portion 112.
Referring now to FIG. 1B, the idealized cross-sectional view of the substrate of FIG. 1A is shown, after photo resist blanket 102a has been partially etched back to a point 102b. As previously described, as the plasma etches away the photo resist, areas on the substrate with a higher topography take longer to etch than areas with lower topography. For example, the amount of photo resist 102b that is remaining in dense regions 115 may be substantially less than the amount of material remaining in isolated regions 116.
Furthermore, the outer edge of the substrate may collect more electrons than the center (hence increasing the corresponding etch rate) since the edge is closer to the plasma potential. For example, the difference in the amount of photo resist 102b that has been etched from dense area 110b (located close to the substrate edge 112) tends to be substantially greater than the corresponding amount of photo resist that is etched from dense area 110a (located close to the substrate center 110). Likewise, the difference in the amount of photo resist 102b that has been etched from isolated area 122b (located close to the substrate edge 112) also tends to be substantially greater than the amount of photo resist etched from isolated area 122a (located close to the substrate center 110).
In addition, photo resist etch back processes may also be susceptible to micro loading and RIE lag issues. Micro loading usually refers to the dependence of the etching rate on pattern density for identical features, and it results from the depletion of reactants because the substrate has a local, higher-density unmasked area. Reactive Ion Etch (RIE) lag is the phenomenon in which narrower features etch slower than wider features. Micro loading and RIE lag issues become even more problematic as requirements for high circuit density on substrates continue to escalate, since they directly impact the performance and function of the substrate.
Referring now to FIG. 2, an idealized cross-sectional view of the substrate in FIG. 1A is shown in which RIE lag has caused the plasma to remove substantially less photo resist in narrow feature 202 than that removed in wide feature 204.
Referring now to FIG. 3, an idealized cross-sectional view of a substrate in FIG. 1A is shown in which microloading has caused the plasma to remove substantially more photo resist in the set of dense features 306 than that removed in isolated feature 308.
In view of the foregoing, there are desired improved methods and apparatus for the optimization of photo resist etching in a plasma processing system.